The non-volatile memories comprise electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash EEPROM, non-volatile static random access memory (NVSRAM) and non-volatile dynamic random access memory (NVDRAM). Every non-volatile memory has its application. For example, the ERAMs with low density (less than 8 K) are used as a consumer radio tuner of a radio or an automotive engine controller. The EEPROMs with middle density is used as changeable softable storage. Thus, these memories have high speed and high reliability memories.
Flash memory has evolved as a low cost alternative to full feature EEPROM, and a more flexible alternative to UV-EPROM, with potential application in the automotive industry (e.g., an electronic engine control), consumer electronics (e.g., a copy machine), data acquisition systems, smart cards, telecommunications, solid state disks, embedded memories, etc. In IEDM Tech. Dig. page 119 on 1990, M. Gill et al. described that a novel tunnel diode was developed for high-density 5V-only flash memories. A low-power memory was proposed in this paper and it developed incorporating this tunnel diode as having excellent operation and reliability characteristics.
EPROMs use channel hot electron injection for byte-programming, and apply ultraviolet light exposure for erasing. EEPROMs employ Fowler-Nordheim (F-N) tunneling for both electrical programming and erasing. Due to the small cell size and simple cell design/process, EPROMs can be produced with higher density and lower cost when compared to EEPROM. On the other hand, EEPROMs offer the capability of byte-erase as well as the convenience of in-system electrical erasability. Recently, the flash memory has gained significant attention as it promises to combine the advantages of EPROM density with EEPROM electrical erasability. In IEDM Tech. Dig., 1990, page 91, B. J. Woo et al. described a flash array contactless EPROM (FACE) technology which can reduce planar areas of the EPROM without further stretching the device limits. Some disadvantages of the prior art for deep-submicron generation were described in this paper. For deep-submicron (&lt;0.5 micron meters) generation, contact printing, definition and associated contact filling, barrier metal and planarization techniques become more complicated. Thus, the FACE technology is used in the manufacture of nonvolatile memories.
The manufacture of EEPROM is to form active regions of the device, a tunnel oxide, a floating gate on the tunnel oxide, an inter-poly oxide on the floating gate and then a controlling gate on the inter-poly oxide. A coupling-ratio characteristic of EEPROM influences the operation of the device. A flash memory with high coupling ratio can be erased or programmed using low power. On page 19 of IEDM Tech. Dig., 1993, Y. S. Hisamune et al. described a high capacitive-coupling ratio (HiCR) cell for future flash memory. The HiCR cell is designed to have an ultra-small tunneling region and a large floating-gate area in order to obtain the high capacitive-coupling ratio of 0.8. The tunneling region has an area of about 0.2 .mu.m.times.0.4 .mu.m and the floating-gate region has an area of about 1.4 .mu.m.times.0.4 .mu.m. The coupling ratio is about 0.8. The cell performance is acceptable for actual device operation in a 3 V power supply.
On page 653 of IEDM Tech. Dig., 1995, H. Shirai et al. disclosed the manufacture of flash memories with a hemispherical grain (HSG) floating gate. The authors of this paper tried to increase the coupling ratio of the flash memory in order to operate the devices by using low power. Not only is the coupling ratio increased, but also few process steps are used in the manufacture of the flash memories. Thus, this simple cell structure promises a low cost 256 Mbit flash memory that works at only 3 V in the paper. Applying HSG poly-Si to the floating gate extends the upper surface area doubling that of the floating gate in comparison with the conventional ones in the paper.
According to the above discussions, increasing a coupling ratio of flash memories and reducing process steps of the devices are an important topics. Many people have tried to solve the problems.